 CMIS 310 Final Study Guide |
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CMIS310 Final Exam Study Guide
(NOTE: "ec" after the question number indicates strong extra-credit potential)
1. T or F: A micro-operation specifies an operation whose result is stored, typically in a register or memory location. Answer = True
Say a few words about the difference in implementing a micro-operation using a direct connection and a bus connection. A bus connection does not require each component to have a direction connection to every other component that they need to talk to. Each component only need connect to the bus (one connection) to be able to talk to any other component connected to the bus. This simplifies design and implementation. A direction connection allows dedicated connections allowing many operations to
2. What does the notation "a:x<-y" mean? Conditions : micro-operations When the condition “a” occurs perform the micro operations (y gets loaded into x)
T or F: Two or more micro-operations can never be performed simultaneously. Answer = False
3. T or F: Sometimes it is necessary to access individual bits or groups of bits within a register. Answer = True
T or F: There is only one basic type of shift micro-operation. Answer = False:There are four basic types of shift operations each of which has two variants(left and right)
4. T or F: A shift micro-operation has two variants, one that shifts left and the other that shifts right. Answer = True
Briefly define the address register and state its purpose. The address register is used to supply the address of the operand being stored or fetched to memory. It is usually preferable to have one connection from the address register to memory instead of having hardwired circuitry perform the operation.
5. T or F: Register transfer language can be used to specify the behavior of any sequential digital system. Answer = True (Can specify from the simplest to the most complex)
T or F: The best use of RTL is to specify the behavior of an entire system, independent of the components used to implement the system. Answer = True
6. T or F: Buses can only be implemented using multiplexers. Answer = False: Buses can be implemented using either tri-state buffers or multiplexers.
Briefly describe a complete design of a system to implement RTL code using a bus and multiplexer. All registers used in the operation would not output their result directly to the bus but instead the outputs would flow into a multiplexor. The multiplexor would have logic to enable the correct register output access to the bus.
7. Take one of the examples (a) modulo 6 counter, (b) string checker, or (c) toll booth controller and explain in words how to convert the state diagram to RTL.
The first step is to create the state table for the specification. The next step is to define all conditions of the state table and their outputs. For the modulo six counter this would be conditions 0 thru 7 corresponding to outputs 000 to 111. You then consider each possible action of the counter in detail and the outputs that it will produce. For example, for each state (S0 to S7) when 1 is added what are the outputs produced. Any unaccounted for states should be created if the output states have a change.
8. T or F: The RTL used in chapter 5 is a pseudolanguage. Answer = True
T or F: Two prominent hardware description languages used by designers are Verilog and VHDL. Answer = True
9.(ec) For X = 1001 1001 0000 0010, show the result of the following operations.
(a) shl(X) Linear shift left (b) shr(X) Linear shift right (c) cil(X) Circular shift left (d) cir(X) Circular shift right (e) ashl(X) Arithmetic shift left (f) ashr(X) Arithmetic shift right (g) dshl(X) Decimal Shift left (Shifts 4 bits) (h) dshr(X) Decimal shift right (shifts 4 bits)
Circular shift requires that the bit that would be moved out is used to replace the other side. Decimal Shift shifts 4 bits left or right instead of 1 (Sign bit does not matter, shifts all bits regardless.
10.(ec) Write valid RTL statements that realize the following transitions. All registers are 1 bit wide. (note: "a" here is same as alpha) a) IF a = 1 THEN copy X to W and copy Z to Y b) IF a = 1 THEN copy X to W; otherwise copy Z to Y c) IF a = 0 THEN copy X to W
a) a: x<-W,Y<-Z b) a: W<-X a’: y<-Z c) a’:W<-X
11.(ec) Indicate in words what the hardware would look like to implement the RTL statements from problem #10.
12. What are the three steps involved in specifying a CPU? 1) First step is to determine the application it will be designed for. 2) Step two is to design an instruction set capable of handling these task. This would include the instructions and registers needed. 3) Step three is to design the state diagram for the CPU showing the micro-operations performed during each state and the conditions that cause state transitions. By specifying these states and operations, the steps needed to fetch, decode and execute each instruction is defined.
13. Give the sequence of operations that a CPU may perform. Fetch Cycle (Fetch instruction from memory) Decode cycle (Determine which instruction has been fetched) Execute Cycle (execute the instruction then go back to fetch cycle)
14. Give some information about the state diagram for the Very Simple CPU. Fetch routines fall through the logic into a series of branch instructions at the bottom of the fetch tree. Each branch taken is based on the top two bits of the IR. Once the branch has taken place each execute tree consists of a series of instructions to perform the desired task. These tasks will include Outputting the address of the instruction to be fetched onto bus. Fetching the instruction from memory and placing it in the DR. Increment the program counter for the next instruction to be fetched. Copy the high order two bits from the DR to the IR (which will be used to obtain the instruction to execute) Copy the low order 6 bits to the AR for routines that need the address. Decode and execute the necessary instructions. Branch back to top of the fetch tree.
15. Give some information about the final register section for the Very Simple CPU. The AR (address register) does not need a connection to the internal bus since it does only supplies its data to memory. The IR (instruction register) does not supply data to any component via the internal bus either so it’s connection to the bus can be removed. The AC (accumulator) does not need a connection to the internal bus again because it does not supply data to any components. The bus is 8 bits wide but data transfers are either 6 bits or two bits. The specification must state which registers send which bits to the bus. The PC (program counter) and the DR (data register) are the registers that need a connection to the bus each via a tri-state enabled buffer.
16. Give some information about the Very Simple ALU. The ALU for the Very Simple Computer performs two functions, the adding of two inputs or the anding of two inputs. Given this design, separate hardware to perform each function is designed. A multiplexor is used to output one of the two results. The Addition is implemented using an 8 bit parallel adder with the AND operation implemented via eight two input AND gates. (Each output connected to a multiplexor)
17. Give some information about the generic hardwired control unit. Hardwired control units use sequential and combinatorial logic to generate the control signals. This control unit is comprised of three components. The first is a counter which contains the current state, second is a decoder which generates signals for each state. The final piece is some combinatorial logic to take each individual state signals and generate the control signals for each component as well as the signals to control the counter. These signals from the logic causes the control unit to trafverse the states in the proper order.
18. T or F: The Relatively Simple CPU has a larger instruction set with more complex instructions than the Very Simple CPU. Answer = True
T or F: The design of the Very Simple CPU follows the same general procedure as that of the Relatively Simple CPU. Answer = True
19. Give and describe some features found in many CPUs that are not found in either the Very Simple CPU or the Relatively Simple CPU.
More internal registers and cache which would replace external memory access therby reducing time needed to execute instructions. Having internal registers also assists in data storage reducing the need for memory access. More buses for routing data between components. Since a bus can only have 1 value at a time on it, multiple buses allow multiple data transfers to occur simultaneously. This reduces the time needed to fetch, decode and execute instructions improving system performance. Multiple buses also eliminates direction connections between components. Many CPU’s incorporate Pipelined instruction processing. This overlapping of fetch, decode and execute (while one instruction is being decoded, the first instruction is being executed while the next instruction is in the fetch cycle.) Having a larger instruction set in a processor’s instruction set allows a program to perform a function using fewer instructions. The drawback to a large instruction set is the time needed to decode the instructions which limits clock speed. Most CPU’s have hardware to handle subroutines, typically a stack pointer and instructions to call and return from the subroutine. These CPU’s also have interrupt inputs to allow external hardware to interrupt the current operations of the cpu.
20. (ec) A CPU with the same registers as the Very Simple CPU has the instruction set and state diagram shown in figure A. Show the RTL code for the execute cycles for each instruction. Assume the RTL code for the fetch routine is the same as that of the Very Simple CPU.
21.(ec) A CPU with the same registers as the Very Simple CPU has the state diagram and RTL code referenced as figure B. Show the instruction set for this CPU.
22. T or F: A microsequencer is not designed as a finite state machine. Answer = False; A microsequencer IS designed as a finite state machine.
T or F: Collectively, all of the microinstructions comprise the microcode, or microprogram, for the CPU. Anser = True;
23. T or F: The microcode memory outputs a microinstruction, the contents of the memory location for that address. Answer = True:
Briefly describe the generic microsequencer organization. The generic microsequencer: A register stores a value that corresponds to one state in the CPU’s state diagram. This serves as the address that is input to microcode memory. This memory location outputs a microinstruction (the contents of the memory location for that address) All these microinstructions comprise the microcode or microprogram for the CPU.
24. T or F: A microsequencer uses mapping logic to access the correct execute routine. Answer = True: The opcode of the fetched instruction is input to the mapping hardware, which converts, or maps, this opcode to the address of the first microinstruction of the instructions execute routine. By loading this address, the microsequencer branches to the correct execute routine. Every microsequencer uses the mapping address to go from the last state of the fetch routine to the correct execute routine
T or F: A microsequencer cannot have subroutines. Answer = False: A microsequencer, like a regular computer program written in high level or assembly language, can have subroutines
25. Briefly give and describe the generic microinstruction format. The format consists of the Select Field, ADDR and Micro-Operations.
Select Field: determines the SOURCE address of the Next Microinstruction(Note that it does not specify the “ACTUAL” address, only the “SOURCE” of the address)
ADDR: Specifies an absolute address. The microsequencer uses this address when performing an absolute jump. (Microinstructions that specify another source for the next address, such as the mapping address, do not use the bits of this field)
MICRO-OPERATIONS: 3 methods 1) Horizontal microcode: First list every micro-operation and assign one bit in the micro-operations field of the microinstruction to each micro-operation. 2) Vertical microcode: Micro-operations are grouped. Each micro-operations is assigned a unique encoded value. Vertical microinstructions require fewer bits than their horizontal microinstructions. Horizontal and Vertical microinstructions require a decoder for each micro-operation field to generate the actual micro-operation signals. The CPU must convert the micro-operation signals to the control signals that load, clear and increment registers, etc. 3) Direct Generations of control signals: This method stores the values of the control signals directly in the microinstruction. This method does not require additional logic to convert the outputs of the microcode memory to control signals, however the code is less readable and more trouble to debug.
26. Briefly describe the design and implementation of a Very Simple Microsequencer. Only two possible next address’s are used, the opcode mapping and an absolute jump. This can be done because the last state of the fetch cycle (FETCH3) goes to one of the four execute routines. (This must be implemented with mapping logic) The remaining states must each go to one specific next state which is implemented using an absolute jump. Each state of the finite state machine is assigned to an address in memory. (The primary consideration is the allocation of address’s for the first state of each execute routine since this determines the logic to implement the mapping function. The microcode must be set up to sequence through these states properly.
27. Briefly describe the use of microsubroutines and microcode jumps in reducing the number of microinstructions. Microsubroutines and the use of nanomemory instructions are used to reduce duplication ie the amount of repetitive instructions. This reduces the amount of memory required to store those instructions. This in turn reduces the size of the microcode memory. Although microsubroutines can reduce and simplify microcode, hardware must be modified to include a register for the subroutines, a way to generate the next address for this register and a way to return to the next address after the subroutine call, all adding overhead and complexity to the control unit. Helps to reduce duplication of redundant microcode, thus reducing the size of microcode memory, and perhaps speeding things up. Issues to consider are resultant complexity, speed of access, and size of nanomemory. 28. Give some issues of microprogrammed control vs. hardwired control.
29. (ec) The Very Simple Microprocessor is modified such that the states are assigned to the following addresses. Show the mapping logic needed for these assignments.
State Address FETCH1 0000 FETCH2 0001 FETCH3 0010 ADD1 0011 ADD2 0100 AND1 0101 AND2 0110 JMP1 0111 INC1 1000
30. (ec) A CPU is specified by the following RTL code. Partition the micro-operations into fields such that the total number of bits is minimized. Each micro-operation OP**2 returns to FETCH1.
FETCH1: AR<--PC FETCH2: DR<--M, PC<--PC + 1 FETCH3: IR,AR<--DR OP001: DR<--M OP002: AC<--AC XOR DR OP011: AC<--AC',PC<--PC + 1 OP012: AC<--AC + 1 OP101: DR<--M,AC<--AC + 1 OP102: DR<--DR + 1 OP111: DR<--M OP112: PC<--PC + DR[5..0]
31. T or F: There are two commonly-used unsigned notations. Answer = True; The first is NON-Negative notation which treats every number as either zero or a positive value. The other approach is two’s complement format in which both positive and negative numbers can be represented.
T or F: In non-negative notation, every number is treated as either zero or a positive value. Answer = True
32. T or F: In two's-complement format, only negative numbers can be represented. Answer = False; Both negative and positive values can be represented
T or F: For the non-negative and two's-complement notations, addition is implemented as a straight binary addition, and is realized in hardware by using a parallel adder. Answer = True 33. Briefly describe arithmetic overflow and the overflow flag. Overflow occurs when the variables being added, result in a amount that can not be represented in that particular variable. For an 8 bit value, overflow would occur if the value is above 255. For Non-negative format the “overflow flag” can be set which is a signal to the rest of the system that an overflow has occurred. For twos compliment notation an overflow can occur with either positive or negative numbers.
T or F: Multiplication can be envisioned as repeated subtractions. Answer =False; Multiplication is repeated additions.
34. Briefly describe shift-add multiplication. Shift-add multiplication takes one value and multiplies it by the least significant digit of the other value, it then multiplies this value again by the next least significant value and so on positioning each successive product one place to the left (shifting) of the previous. These intermediate values are then added together producing the result.
T or F: Division can be envisioned as repeated additions. Answer = False; Division is repeated subtractions
35. Briefly describe signed-magnitude notation. Signed-magnitude notation has two parts. The first part is a sign part which = 0 for positive and 1 for negative. The second is the magnitude part which holds the absolute value for the number in the same format as unsigned non-negative numbers.
36. Briefly describe signed-two's complement notation. Signed-two’s complement notation is similar to signed-magnitude in which there is a sign part and a magnitude part. The difference is that the magnitude part is stored in two-s complement notation instead of the absolute value. The positive values are the same in both signed-magnitude and signed-two’s complement.
37. Briefly describe binary-coded decimal format. BCD has 4 bits for each decimal numeral. Multi-digit numbers are stored as multiple groups of 4 bits per digit. To represent any number above 10 and less then 100 requires two 4 bit values (8 bits)
38. Briefly define a)pipelining and b) lookup table. Say a few words about each. An Arithmetic pipeline is similar to an assembly line. Data enters a stage of the pipeline which performs some arithmetic operation. The results of that stage are then passed along to the next stage which performs its operations and so on until the final computation. Each stage performs only it’s specific function and not that of any other stage. A pipeline does not speed up individual computation. It improves performance by overlapping computations (each stage can operate on different data simultaneously.
Lookup Tables: Any combinatorial circuit can be implemented by a ROM. The inputs to the combinatorial circuit server as the address inputs to the ROM. The outputs of the ROM correspond to the outputs of the circuit. The ROM can be programmed such that values are generated for output for any possible values used for input. The downside is that the size of the lookup tables grouws rapidly as the size of the operands increases.
39. Give some info about floating-point numbers. Floating point is very similar to scientific notation. There is a “sign” a “significand” and an “exponent”. Floating point numbers must be normalized which means that the significand has no leading zeros. A special value is assigned to zero and algorithms must check for this number. NaN or (not a number) must also be accounted for and checked for. Computers store floating point numbers in a predefined format. Each number has a 1 bit sign, a significand of predetermined length and an exponent of a given length. Since the exponent has no sign a “bias” must be added to the exponent before the algorithm generates it’s result. Floating point precision characterizes how precise a floating point value can be and is defined as the number of bits in the significand.
40. (ec) Give the two's complements of the following values. Each number is represented as an 8-bit value. a) 64 b) 33 c) -1
Two’s complement is achieved by taking the inverse of each bit and then adding 1 to the result. For example 1001 = (0110 + 1) = 0111 in two’s complement.
41. (ec) Show the representation of the following values in unsigned non-negative notation and unsigned two's complement notation. Each number is 8 bits. a) 29 b) -128 c) 199
Non-negative notation represents each value as a positive result. Un-signed two’s complement is writing it in two’s complement. For -128 the value would be 1000 0000
42. (ec) Show the representation of the following values in signed-magnitude notation and signed two's complement notation. Including the sign bit, each number has a total of 8 bits. a) -63 b) 147 c) 85 Signed Magnitude signed two-s complement a) 1 00111111 1 11000010 b) 0 10010011 0 01101101ß Check this answer (I used 2s compliment) c) 0 01010101 0 10101011ß Check this answer (I used 2s compliment)
Signed-magnitude has a sign bit AND the number in its absolute form exactly like a non-negative number. Signed two’s complement has a 1 bit sign and then the magnitude for a negative number is stored in it’s two’s complement. (Positive values are stored exactly as in signed-magnitude.)
43. T or F: A computer system is always constructed using a single type of memory. Answer = False: Several types of memory are used:
Briefly give the memory hierarchy. Cache memory is situated closest to the microprocessor. (A cache controller copies data from physical memory to cache memory) Cache memory has two levels. L1 Cache is incorporated directly into the microprocessor. L2 Cache is usually outside of the microprocessor. Physical memory or DRAM is the most well known and is constructed for dynamic random access. As processor speeds increased, physical memory becomes a bottleneck. Virtual memory is on a disk drive. Swapping of data between physical memory and this virtual memory is performed by a virtual memory management routine. The closer the component is to the processor the faster and more expensive it is.
44. T or F: In the memory hierarchy, cache memory is situated closest to the microprocessor, since it is preferable to fetch instructions and data from this faster memory. Answer = True
T or F: Cache memory only has one "level". Answer = False; Cache memory is hierarchical with L1 and L2.
45. T or F: The goal of cache memory is to maximize the processor's access time. Give some info about associative memory. Answer = False; The goal of cache memory is to MINIMIZE the processor’s access time.
Associative memory is accessed differently then regular SRAM (which is accessed by memory location). To access associative memory, a portion of the data is specified. Associative memory then searches all it’s locations in parallel and marks the locations that match the specified data input. The matching data values are then read out sequentially. To read from associative memory, the cpu must specify the data to be matched (Argument) as well as which bits of the argument are to be checked (Mask).
46. Briefly describe the three mapping techniques associated with cache memory. Associative mapping has the cache keep the address of physical memory adjacent to the actual byte of data. Given 8 bit memory, and 64K of total memory, the cache would consist of 24 bit wide sections. In each section the first 16 bits would be the actual address of memory with the final 8 bits the data stored at that location. When the CPU needs access he will output the mask with the 1st 16 bits set to 1 with the low order 8 set to zero. If the data is in the cache and valid then the low order bits are loaded into the output register. If not then the data must be fetched from physical memory. This type can also be used to fetch blocks instead of bytes. With associative mapping with blocks, the memory required is larger bit reading in blocks of data as opposed to bytes means less possible direct reads from memory.
Direct mapping can use static SRAM which is cheaper than associative memory. Direct mapping uses an index and tag field to check address locations. The tag field is used to supply the upper portion of memory address while the index points to a particular piece of cache. Each piece of cache contains 3 fields. The tag field, the data stored and the valid bit. Once an index matches, the tag is checked for exact memory address and if valid this contains the data needed. If the tag or valid bit do not match, then the data must be fetched from physical memory. Direct mapping can also utilize reading blocks of data which will take advantage of locality of reference. With direct mapping, EACH WORD OF PHYSICAL MEMORY CAN BE MAPPED TO ONLY ONE SPECIFIC LOCATION.
Set-Associative mapping makes use low cost SRAM and is similar to direct mapped cache, except each address in the cache can contain MORE than one data value. Each location contains two groups of fields, one for each way of the cache. Since each cache location contains two groups a 1K cache has 512 locations. Set associative mapping has a tag field, the data field and the valid flag similar to direct mapping. The valid/count field servers two purposes, one purpose is for valid data flag while the other keeps track of when the data was accessed.
47. Define a) locality of reference, b) block of data, c) index, and d) tag.
Locality of Reference: When an instruction at memory location X is accessed, it is very likely that the next instruction to be executed will be at location X + 1. If blocks of data are loaded into cache as opposed to one byte, locality of reference says each subsequent byte will most likely be needed.
A TAG field is used with direct mapping and contains the high order bits that combined with the index maps directly to a position in physical memory.
An INDEX is used to specify ONE specific location in the cache. This index must be large enough to address every location within cache.
A BLOCK of DATA is a portion of memory that is contiguous and loaded into cache in consecutive positions.
48. Give three techniques for replacing data in the cache. First In First Out, Least Recently Used, and Least Frequently Used
49. Give two techniques for writing data to the cache. Write-through and write-back
Describe some issues re: cache performance. Cache hits – the CPU checks cache for the data. If the data is there a cache hit is recorded Cache miss – when the CPU makes a request for data and the requested data is not in a cache a cache miss is recorded and the data is retrieved from physical memory Hit ratio – percent of cache hits to misses. Higher percent of hits means better performance Avg. memory access time – a weighted average of cache access time plus physical memory access time
50. T or F: Virtual memory swaps data in and out of physical memory. TRUE
T or F: Virtual memory makes it appear to the CPU that there is less physical memory than is actually present. FALSE
51. Briefly define a) memory management unit, b) swap file, c) logical address, and d) physical memory address. a) MMU – moves data between physical memory and a slower device (i.e. a hard disk) b) the storage are on the slower device used for memory (i.e. hard disk) c) The location of data as kept by the MMU d) The actual location of the data on the storage medium
52. Give some information about paging.
53. Give some information about segmentation and memory protection.
54. (ec) For the 16 x 8 associative memory whose contents appear in the following table, what values should be stored in the data and mask registers to select the last location? Assume the first 8 bits are a tag and the rest are data.
Data Valid 0000 1001 0010 0111 0 1011 0110 0011 0001 1 0101 1111 1100 0000 1 1101 0110 0111 1000 1 0000 0000 0000 0000 1 1111 0000 0111 1111 0 0110 1111 1000 0000 1 1111 0000 1111 0000 1
Data value should be 1111 Mask value should be 1111 0000 0000 0000
55. (ec) Show the layout of a cache for a CPU that can address 1M x 16 of memory; the cache holds 8K x 16 of data and has the following mapping strategies. Give the number of bits per location and the total number of locations. a) fully associative b) direct mapped c) two-way set associative
56. (ec) A computer system using the Relatively Simple CPU is to includea 1K associative cache with a line size of 2 bytes. a) How many bits are in each location of the cache? Answer = 30 since a 4 byte line has 46 bits b) What mask value is needed for the associative memory? The mask will be 15 bits instead of 14 bits. 0111 1111 1111 1110
57. T or F: The address bus is output from the CPU and read in by the I/O device interface.
Give some info about the connections between a CPU and an I/O device.
58. Give the difference between asynchronous and synchronous data transfers.
Summarize the difference between source-initiated and destination-initiated data transfer.
59. Give some info about handshaking. T or F: The function of programmed I/O: A program instruction causes the CPU to input or output data.
60. T or F: Programmed I/O is always memory-mapped (never using isolated I/O).
T or F: Input/output devices are slower than memory, and the amount of time they require may vary.
61. Briefly describe the concept and benefits of interrupts.
62. Describe the architecture of a computer system with DMA.
63. Give some other info about direct memory access (DMA).
64. Summarize some facts about I/O processors. I/O processors handle all of the interactions between the CPU and I/O devices. 1 I/O processor can coordinate transfers from several different I/O devices The CPU has direct interaction with the I/O processor, the CPU sends instructions for the I/O processor to perform tasks between itself and the I/O devices. The CPU coordinates it’s own transfer of data between itself and the I/O processor Commands carried out by the I/O processor: block transfer commands, moves blocks of data. Arithmetic, logic and branch operation commands used in manipulating data. Control commands, hardware dependent and issued to control the system
65. Summarize some facts about serial communications. Serial communications are used to transmit more that one bit of data at a time. CPU’s almost always do not communicate directly with a serial device, they use parallel communications and convert the data. 2 major modes of serial communication in the text are asynchronous and synchronous.
Asynchronous is used to communicate with peripheral equipment and does
not share a common clock. It must therefore have a set transmission
speed(bps) and number of data bits per transmission. Without these
agreed upon parameters corruption or loss of data will occur. Also
there must be an agreement of parity bits if used and stop bits. Each
byte of data is transmitted separately.
66. (ec) Show the state diagram and RTL code to implement the OTPT instruction, with instruction code "0010 0001 F", and operation "Output port F<--AC". (Note: F here is the same as gamma)
67. (ec) Given the following sequence of events, show which routines the CPU is executing for times 0 to 100 ns. Each handler routine (with its interrupt request) takes 20 ns to complete.
Time Action 0 ns Start of main program 10 ns IRQ1 20 ns IRQ2 45 ns IRQ3 60 ns IRQ4
Main 0 – 10ns
IRQ1 10-20ns Main 90-100ns
68-75. Write a short paragraph describing something you learned in the course and how it may be of benefit to you in the future.
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